Mobile processors have recently been required to realize low power consumption and high performance. In order to satisfy these requirements, a scheme called “DVS (dynamic voltage scaling)” is currently used. DVS is known from, for example, the following Non-Patent Documents 1, 2, and 3. DVS dynamically changes clock frequency and power supply voltage in accordance with a required battery duration or processor load. When the required battery duration is long or the processing load is low, the clock frequency is lowered, and the power consumption is reduced. Further, delay of signals is adjusted so as to match a prolonged clock cycle time, and power supply voltage is lowered. Thus, the power consumption during execution of programs is reduced. Although DVS is an effective method for reducing power consumption, its effectiveness will diminish in future processing techniques, from the viewpoints that decreasing threshold voltage becomes difficult because of an increase in subthreshold leakage current, and that transient faults increase.
As an alternative, a method called “pipeline stage unification (PSU)” has been proposed as disclosed in the following Non-Patent Documents 4, 5, and 6. Although PSU is simple, it can reduce power consumption effectively. As in the case of DVS, PSU lowers clock frequency so as to reduce power consumption of a processor. However, unlike DVS, PSU does not lower the power supply voltage, but unifies a plurality of pipeline stages by bypassing pipeline registers. PSU can reduce power consumption by means of the following two phenomena.
First, the total load of clock drivers can be reduced by stopping supply of clocks to the bypassed pipeline registers. Further, since the pipeline registers for which supply of clocks is stopped do not operate, power consumption can be reduced by an amount corresponding to power consumed through operation of D-FFs. Second, due to unification of pipeline stages, the pipeline of a processor becomes short. As a result, the number of clock cycles required to execute a program becomes equal to or less than that of a processor which operates at the same clock frequency and uses DVS, whereby a time period in which power is consumed can be shortened. For example, penalties from branch prediction misses are reduced by reducing the number of pipeline stages of an instruction fetch portion and a decode portion of a front end pipeline portion, whereby the number of execution cycles is reduced. The above-described effects are expected.
Meanwhile, Patent Document 1 listed below discloses an apparatus which changes the number of pipeline stages in accordance with clock frequency. That is, when high-speed processing is required, processing is performed at a high clock frequency in a large number of stages so that only a small difference in processing time is produced among these stages. When high-speed processing is not required, processing is performed at a low clock frequency in a small number of stages so that the number of penalties from branch interlock decreases, and power consumption decreases.
Patent Document 2 listed below discloses a processing apparatus which includes a plurality of modules and in which, for each instruction word, supply of clocks to unused modules is stopped so as to reduce power consumption.
Patent Document 3 listed below discloses a method of estimating power consumption of a processor. Patent Document 4 listed below discloses a technique for increasing and decreasing the clock frequency of a CPU so as to increase a performance index within a given power consumption index range.
[Non-Patent Document 1]
D. Laird, “Crusoe Processor Products and Technology,” Transmeta Corporation, 2000.
[Non-Patent Document 2]
Intel Corporation, “Intel Pentium M Processor Datasheet,” 2003.
[Non-Patent Document 3]
Advanced Micro Devices, Inc., “Mobile AMD Athlon 4 Processor Model 6 CPGA Data Sheet,” 2001.
[Non-Patent Document 4]
So Shimada, Hideki Ando, Toshio Shimada, “Variable Pipeline for Lowering Power Consumption,” Research Report of Information Processing Society of Japan, Vol. 2001-ARC-145, pp. 57-62, 2001.
[Non-Patent Document 5]
So Shimada, Hideki Ando, Toshio Shimada, “Pipeline Stage Unification: A Low-Energy Consumption Technique for Future Mobile Processors,” Symposium on Advanced Computing Systems and Infrastructures, SACSIS2003, pp. 283-290, 2003.
[Non-Patent Document 6]
Hajime Shimada and Hideki Ando and Toshio Shimada, “Pipeline Stage Unification: A Low-Energy Consumption Technique for Future Mobile Processors,” In ISLPED2003, pp. 326-329, 2003.
[Patent Document 1]
Japanese Patent Application Laid-Open (kokai) No. H9-319578
[Patent Document 2]
Japanese Patent Application Laid-Open (kokai) No. 2005-234968
[Patent Document 3]
Japanese Patent Application Laid-Open (kokai) No. H11-161692
[Patent Document 4]
Japanese Patent Application Laid-Open (kokai) No. H11-353052